This invention relates to a CMOS logic circuit.
As an example of a CMOS logic circuit related to this invention, a circuit of three input CMOS NOR gate is shown in FIG. 1.
Between a power supply voltage VDD terminal and an output terminal 107, P-channel type MOS transistors 101-103 are connected in series. Further, between output terminal 107 and ground voltage Vss terminal, N-channel type MOS transistors 104-106 are connected in parallel. This NOR gate is advantageous in that static direct current (dc) is not consumed, resulting in small power consumption.
The configuration of another three input NAND gate related to this invention is shown in FIG. 2. In this gate, in a manner oppositely to the NOR gate shown in FIG. 1, P-channel type MOS transistors 111-113 are connected in parallel and N-channel type MOS transistors 114-116 are connected in series.
When a comparison between a NOR gate shown in FIG. 1 and a NAND gate shown in FIG. 2 is made, the NOR gate has a lower operation speed in the case where transistors of the same dimensions are used. This is because P-channel type MOS transistors 101-103 are connected in series in the NOR gate, so it takes much time for charging the output terminal 107 by these transistors 101-103. On the other hand, in the case of a NAND gate, since N-channel type MOS transistors 114-116 are connected in series, but the carrier mobility of an N-channel type MOS transistor is greater than that of a P-channel type MOS transistor, the speed for charging the output terminal 117 is high.
In order to cope with the problem that charging speed in a NOR gate is low, the technology in which static dc is used to realize high charging speed is disclosed in the following literature.
"A Symmetric CMOS NOR gate for high speed application" (IEEE Journal of Solid State Circuits, Volume 23, No. 5 October 1988, pages 1233-1236).
In this literature, the symmetric CMOS NOR gate as shown in FIG. 3 is disclosed. A symmetric CMOS gate refers to a gate in which even if replacement is made in connection with a P-channel type MOS transistor and N-channel type MOS transistor, the configuration of the circuit is not changed.
In this gate, there is no series connection of P-channel type MOS transistors, and P-channel type MOS transistors 121-123 are connected in parallel between power supply voltage VDD terminal and output terminal 127. This configuration corresponds to the configuration in which output terminals of three CMOS inverters are short-circuited.
When data of logic "0" level is inputted to the gates of all P-channel type MOS transistors 121-123 and N-channel type MOS transistors 124-126, three P-channel type MOS transistors 121-123 are turned ON. Namely, output terminal 127 is charged by three P-channel type MOS transistors 121-123 connected in parallel. Thus, this NOR gate operates at a speed higher than that of the NOR gate shown in FIG. 1.
However, the NOR gate shown in FIG. 3 has the problem that power consumption is large. When N-channel type and P-channel type MOS transistors are turned ON at the same time, current flows directly from the power supply voltage VDD terminal to the ground voltage Vss terminal. Although this NOR gate has three input terminals, if a larger number of inputs is provided, power consumption is further increased accordingly. Namely, the problem that power consumption becomes larger with increase in the circuit scale becomes more serious.